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Clock Tree Synthesis


All clock nets were regarded as ideal nets prior to this stage. This indicates that the placement optimization command has not optimized them. Optimization of placement would only put them. However, CTS is completely free to alter the positioning that has already made. Additionally, all clock nets and cell delays are taken to be zero from a timing perspective. As a result, there will be no clock skews. You have now completed the CTS, which involved creating a clock tree on highly fanning clock nets and optimizing clock pathways. Reducing clock skews, minimizing clock insertion delay (also known as clock latency), and correcting violations of the maximum cap/slew are the tool's objectives (logical DRC’s on clock nets).

You would have to define targets for the CTS tool before you could begin to execute the actual clock tree synthesis commands. These objectives also serve as CTS objectives. These are the following: global clock skew, smallest insertion delay, highest capacitance, highest slew, and highest fanout.

Goals for CTS

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