Global Clock Skew
In a perfect world, all clock signals would arrive simultaneously at the clock pins of flops. In this instance, there is no clock skew. Clock skew is the temporal discrepancy between the clock signals' arrival times at each flip-clock flop's pins within a clock domain. The discrepancy between maximum and minimum arrival times across all flip flops is known as the global skew. Depending on the tool you use, you must set the global clock skew as the target for the CTS tool.
The tool will attempt to create a clock tree that is balanced and has the least amount of clock skew possible.
Minimum clock insertion delay or clock latency
A delay from the clock root to the clock endpoint is known as clock latency or clock insertion delay. The end of the clock is the endpoint. This is typically one of the following: a clock pin or macro, a clock output port on the design, the clock pins of a sequential element like a flop, latch, or integral clock gater, etc. The default clock end points are these. Through CTS limitations, you can also define another pin as the clock end point.
The tool attempts to reduce the clock tree's average latency under the existing circumstances. However, the tool will add some buffers at the root to make the insertion delay to the required insertion delay if you want these latencies to be larger than what CTS achieved. The tool will not operate if the insertion delay is less than what it is capable of. If you believe there is a significant clock insertion delay, you should investigate the cause. And in order for the tool to reduce clock insertion delay, you would need to adjust some settings or make some exceptions. Look for clock path timing reports, analyse them in a GUI, and determine what is happening. Issues may be caused by tighter slew, cap, and skew limits.
Logical DRC's
These are maximum net capacitance, maximum slew visible on pins, and maximum fanout. CTS will make an effort to achieve these objectives. Here, you ought to include some sensible upper limits. Making them really tight will result in high latencies and overbuffering.
Along with defining the clock skew targets, you might also need to consider whether you should direct the tool to create some unique balancing criteria. These include:
Changing the balance of clock endpoints by adding or eliminating them.
Creating some endpoints that are balanced individually from the remainder of the standard clock endpoints. It is known as a separate skew group in most cases.
Establishing a latency link between select endpoints and the default clock group.
Making some endpoints part of a completely distinct clock tree, hence lowering latencies to those endpoints
Balancing multiple clocks together
In every tool, you can set these exceptions or limits. These are either carried out if you are aware of the requirements in advance or if you notice problems with clock skews, latencies, or setup/hold times
Post CTS timing optimization
After doing CTS, clock routes will really have cell and net delays. "Clock propagation mode" is the name given to this mode. In this scenario, clock skew will cause timing issues and you will start experiencing clock delays. Setup may not be significantly changed, but hold will be greatly affected. Hold fixing for the initial timing in the flow is thus a crucial timing optimization step. In order to correct hold violations, you will perform incremental timing optimization steps here, including optimization setup and buffering.