The power supply (VDD and VSS) in a chip should be uniformly distributed through the metal rails and stripes termed as Power Delivery Network (PDN) or power grid. Each metal layers utilized in PDN has finite resistivity. When current flows through the power delivery network, a part of the applied voltage will drop due to the metals internal resistance. As per the Ohm’s law, the amount of voltage drop will be V = I.R, called as IR drop.
Standard cells or macros sometimes do not get the minimum operating voltage which isrequired to operate them due to IR drop. This drop may cause the poor performance of the chip due to the increase in delay of standard cells and may cause the functional failure of the chip due to setup/hold timing violation. To avoid this issue, IR analysis must be done and consider its effect in timing analysis in the design cycle.
IR Analysis Tools
Checks perfomed in IR analysis