Physical Only Cells

Well Tap Cells

The standard cells in higher technologies were designed with the n-well connected to the VDD and the P-substrate connected to the VSS.
As technology advances, it has become clear that each typical cell does not require an n-well connection to VDD and a P-substrate connection. Each standard cell row can have it attached at regular intervals.
To prevent the latchup issue, tap cell will be placed.
Tap cell is having connection of VDD and VSS, where n-well is connected to VDD and P-substrate is connected to Vss.
Tap cells reduce the resistance between the VDD and VSS to well of the substrate.

Tie cells are special purpose standard cells, which are used to provide constant high or constant low voltage.

As the technology shrinks, the gate oxide becomes thinner and thinner, it will become more sensitive to the power supply, even a small amount of change in the voltage can results in the damage of the gate oxide it leads to the damage of the transistor.
To prevent the damage of the transistor tie cells are used.
Tie cells output have a constant high or constant low, there won’t be any voltage surge in output of tie cells.
Tie high provides constant high, and Tie low provides constant low.

Endcap cells are don’t have any logical pins, they have only VDD and GND connections.
Endcap cells are placed at the end of the standard cell row.

The standard cells' gate, which is positioned at the CELL's boundary, has the potential to be damaged.
To prevent this, an alternative approach to the one used in the previous paragraph is employed.
A dummy gate is attached to the standard cells, and if there is potential damage to the standard cells, only the dummy gate gets damaged, and the cells are protected.

Filler cells are physical only cells, and they don’t have any logical function and they are used to provide the continuity of the N-Well, Implantation layer and Power Continuity.

We won’t have to generate every new mask because finding a mask that will fit everything might be very difficult.
If we use some of the original masks and higher the size of mask, it will hard wait to get them made.
In standard cell row, there is a gap between the standard cell, it leads to the N-Well discontinuity and these discontinuities will leads to the DRC violations.
And also, due to this discontinuity in the N-Well, the tap cells will be missing.

Decap cells are essential capacitors that holds the charge and that are placed near the power-hungry cells.
Whenever, the cell switches the decap cells start discharges and provides the constant current to the cell and keeps the power supply constant.

When the power supply is far away from a particular cell and by the time Vdd reaches to it,a small amount of voltage drop across in both Vdd and Vss which effects functionality of the cell.
The Voltage drop is due to power and ground rails, are nothing but metal wires and these are having resistance and inductance values.
As we know the voltage is function of current and the inductance. So, when the current flows through the metal wires, it sees the voltage drop.
Now, this voltage drop is greater than the noise margin of the cells, that might lead to the improper functionality of the cell.

Spare cells are used to implement ECO after Base-to and Metal-to if any bugs reported after the tape-out, we could use these spare cells to fix the bugs.
Spare cells are nothing but std cells and are placed across randomly across the design.
Cells which are required to keep input pins tied down should have the pins tie-down control pins connected to VDD/VSS, but if they have to be used, the cells’ input pins should be disconnected from VDD/VSS and connected to the logic circuits in ECO.

ICG cells are used to save the power.
ICG cells basically stop the clock from switching, sometimes stopping clocks in a big group of logic cells, when we apply a low clock enable signal on it. This phenomenon is known as Clock Gating.