Placement

Introduction

After finishing floorplanning and powerplanning you can do std cell placement and optimization to achieve various design goals. Design goals can be timing, power and area. Placement optimization tries to achieve these goals making sure that design is routable as well while doing placement of cells. In nutshell tool will first do placement of cells, high fanout buffering, logical restructuring to meet timing, Cell sizing, buffering, cloning, vt swapping for leakage optimization, area reduction. Different tools follow different orders for the above steps. The database at the end of placement optimization would be a legally placed and optimizes design.

Depending on your analysis post placement optimization, you may decide to move forward and take step back. The step back can be from floorplanning or redoing placement depending on your analysis.

The basic steps of a standard cell placement and optimization are

Generate floorplan
Calculate timing
Calculate power
Pre-route cells (cell placement and routing)
Place cells (optimization)
Route cells (pull-up routing)
Optimize timing
Optimize power

If you have a dedicated floorplanning tool, you can just run it and it will do most of these steps for you (the ones it can't do you can do manually).

After you’ve finished the initial floor planning you can distribute your power buses and cell sizes. Adjusting placement to meet timing estimates requires making sure that the design meets timing and does not become unroutable. Design goals can be time, power, area, routability. Layout optimization optimizes timing, cell sizing, buffering, logical restructuring to meet current timing, Cell sizes, buffer, cloni ng, vt swapping to meet leakage models.

Perfomance

Performance specification includes both the timing constraints and the placement constraints.
A timing model is needed to model the frequency or the timing at which a register is arriving at an I/O port.
A Placement model needs to be developed before we can start modelling the timing.
Reliability model is just about analysing whether every timing constraint will be met after placement. This field is direction less. It requires no optimization techniques.

Logical DRC's

Apart from the setup and hold time, will also look for logical DRC fixing.
Slew is currently defined as 100% and capacitance limits are typically established very conservatively to ensure there is no overshoot. It is not a hard limit as long as these are not violated.
Typically, a period of ramp up and ramp down comes to an ending weight. This ending weight helps protect equipment from long term load relaxation. But you can see with experience that in many cases this is already not the best choice. It is good to first bring other QoRs to 100% and then do a complete DRC.

Routability and Congestion

While achieving completion strategies (or other objectives), tool always makes sure that the overall design remains routable.
It seeks to achieve a noteworthy reduction in congestion through the process. It keeps placement within a design as well as the wirelength under control.
Tool deploys various techniques to reduce congestion. While it may have to sacrifice some wire length to achieve fulfilment, it seeks to somehow reduce congestion.

Area

This is an optional goal for placement optimization. Placement tool will try to reduce the device area by trying to reduce the cell size.
However, a die size is already provided! The die size you are assigned will be the die size you get from the fab. The same die size will be used in subsequent iterations. Reducing die size will reduce the silicon area.
You can also look for a balance between area reduction and power reduction. You could try optimizing design for area reduction with a goal of reducing power slightly. Power is considered in subsequent iterations.

Leakage power

This is a trade-off for a goal for placement optimization and is done only if configuration settings are provided to optimize leakage power.
In every latest technology, customers get multiple Vt libraries available to choose from. Vendors provide a minimum of two Vt versions of libraries. Vt is (Voltage threshold of the transistor). So, low Vt leads to low leakage power, and higher Vt leads to low speed. If Vt is low, leakage will be high.
If you want to achieve a high speed, you would want to use cells with low voltages so as to increase current. The problem with this approach, however, is that the heat caused by this higher current can overheat your chips and must be limited.
In addition, this high-current system has a greater chance of creating DRCs because of its higher power. Unlike our IC counterpart, GDS uses only one version of these low Vt cells to be placed on your design without creating DRC errors. The principles of GDS use the same principles of transistor sizing upwards.