Verification of RTL designs occupies an important role in the VLSI design flow.
Functional verification is one approach to ensuring quality.'Quality' refers to the state of the product where it performs as intended under various operating conditions.
This is how the chip manufacturing flow goes-
Verification is a process in which a design is verified against a given design
specification before chip tape-out. This happens along with the development of the design and can start from the time the design architecture/micro architecture definition happens. The main goal of verification is to ensure functional correctness of the design before the tape out.
Validation is a process in which the manufactured chip is tested for all functional correctness in a lab setup. This is done using the real chip assembled on a test board.
On a side note, join the Upcoming D.V demo on 19th November, where we will share even more cool stuff about DV.
And on a even more interesting side note, we are starting a Design Verification batch on 28th November. Which you can enquire about using the below link