RTL Design is a functional prototype of a chip. It must go through rigorous
testing before moving to the next phase. Most of the bugs in a chip are either logical
or functional. Verifying for corner cases will bring bugs to the surface. These are
difficult to find with basic checks alone. RTL Verification involves review of design
specifications, Planning the verification items / scenarios and building a test bench.
RTL Design complexity has increased significantly over the time.
Verification of the design early in the flow is highly desirable.
Functional verification involves not only finding obvious bugs, but also hunting down deep rooted bugs by verifying for as many as corner cases as possible. 60% of the time is spent in Design Verification to find and fix the design bugs using Functional Simulation and eliminate them at the earliest.
Obvious bugs are detected by checking basic cases. Deep rooted bugs occur when corner cases are invoked. They can be difficult to find and fix. And this further increases the number of corner cases.