Logical World to Physical World
The VLSI Chip design includes different types of processing steps to finish the entire flow. For anyone, who just started his career in VLSI physical design flow. Each and every step of the VLSI physical design flow has a dedicated EDA tool that covers all the aspects related to the specific task perfectly. All the EDA tools can import and export the different file types to hel
p making a flexible VLSI design flow that uses multiple tools from different vendors.
Physical Design is a Process of Transforming Netlist(Logical Design) into GDSII (Layout Design) format which can be fabricated in a foundry. During Physical Design, certain performance parameters are ensured for the correct performance of the circuit and manufacturability
of the circuit like Timing, Power, Performance and Area.
Main steps in physical design are floorplan, placement of all logical cells, clock tree synthesis & routing. During this process of physical design area, timing, power, design & technology constraints have to be met. Further design might require being optimized with respect to area, power, timing and performance.
Stages — Floorplan
— Powerplan
— Placement
— Clock Tree Synthesis (CTS)
— Routing
— Signoff Checks
Objectives — Timing
— Congestion
— Area
— Power
Possible Issues — Timing Violations
— Congestion Issues
— Design Rule Violations
Inputs to Physical Design
Basically there are three types of input views
1. Logical View
2. Timing View
3. Physical View
1. Logical View Contains — Verilog netlist (.v)
— Standard design constraints (.sdc)
— Unified power format (.upf)
— Design exchange format (.def)
—Scan chain reordering file (.scandef)
2. Timing View Contains — Liberty File (.lib)
3. Physical View Contains — Library exchange format (.lef)
Before Going to Floorplan first we need to check all the inputs of physical design. this process is called a sanity checks
Sanity checks —Assign statements shouldn’t be exist
—Floating input pins and floating output Ports shouldn’t exist
—Tristate buffers shouldn’t be exist
—Multi-driven inputs shouldn’t exist
—Combinational loops shouldn’t exist
—Check whether clock definitions are missing or not, each and every clock in
our design should be defined in sdc, if clock definition is missing then clock is treated as data
—Checks on clock exceptions and check whether they are defined or not
—Checks on Design rule Violation constraints and check whether they are
defined or not
Checks on External Delays and check whether they are defined or not
Floorplan : It is a Process of Placing Macros and Standard Cells(preplaced cells) in a core area based on hierarchy and flow chart by following some macro guidelines.
STEPS IN FLOORPLAN
—Size & Shape of the Die is decided
( Aspect ratio & core to io boundary is decided) Aspect ratio = width / height
—Core utilization is decided
—Macro Placement. ( according to data flow )
—IO port Placement. ( according to data flow )
—Creating Standard cell row
— Adding physical cells. ( ESD, ICOVL, TCD, WELLTAP, ENDCAP )
PowerPlan : It is a process of Creating a power mesh and supply a power to the every macro, cells which are present in a design.
STEPS IN POWERPLAN
—Creating Power Ring
—Creating power stripes
—Creating Via’s
—Creating Follow pin
—Connect pg nets
Placement : It is a process of placing standard cells in the design.
STEPS IN PLACEMENT
— Coarse placement
— Global placement
— Legal placement
— Placement Optimisation
Types of Placement
—Timing Driven Placement
—Congestion Driven Placement
Clock Tree Synthesis (CTS) : It is a process of building a clock tree in the design
Goals of CTS
— To have Balanced Skew
— To have MIninum Latency
Routing : It is a process of making Physical connection
s based on logical connectivity between macros, cells, I/O pins.
STEPS IN ROUTING
— Global Routing : does congestion analysis and dirty routing.
— Track Assignment : each net is assigned to tracks
— Detailed Routing : actual routing is done between the cell pins
— Search and Repair : searches for routing violations and repairs
The Physical Design plays a crucial role in VLSI chip design. It involves the translation of a circuit’s
Logical description into a geometric representation, which can be fabricated on a semiconductor chip. So, the importance of physical design in VLSI is more.