Timing Optimization | Starvlsi Blogs

Cell sizing

To meet timing and area requirements, standard cells will be resized. Each standard cell type will have at least 4-5 sizes. The tool will select the appropriate size.
To save space in critical paths, the tool may select the smallest or almost smallest size buffers. Selecting up the smallest cells is usually not a good idea. The smallest cells will cause a slew of issues.
Crosstalk and congestion are two of these issues. When the size of complex cells is lowered, the pin density increases, allowing huge numbers of pins to be routed in a limited space, producing local congestion.
When smaller cells are utilised in non-critical paths, they provide a weak drive and a high slew that is sensitive to high crosstalk. For both noise and delay, high crosstalk might be problematic. Consider hiding (rather than using) the smallest drive cells. If you notice congestion in small places and it appears that the tool is using small size complex cells, small drive complex cells should be hidden as well.

Placement Steps

Timing optimization

Vt swapping

Tool can be specified for power consumption optimization. Tool can swap cells to a different cell library with different Vt with lower leakage power consumption.
Turning leakage optimization on automatically can be done two ways. First is by putting more slower cells in early on
when leakage start to dominate the design and use only high speed cells for the rest of the design lifetime. The other way is to decide which cells should be so "fast" early on. This option would lead to certain cells being replaced by faster cells before the design turn on leakage optimization.

Logical restructuring

To meet a timing tool, one should optimize the timing and area of a design.
A timing tool can also do multiple things like breaking complex cells into simpler ones or vice versa.
Pin swapping, as well as other logical restructuring without
changing the functionality of the design is possible.

Cloning

PnR tools can perform cloning of cells to reduce fanout. Sometimes it is beneficial to perform cloning rather than buffering.
Reducing fanout allows the servo/s to leverage the PnR tool (without buffering).

Buffering

PnR tool does buffer based on some estimations of how long a net buffer can drive. It can even revisit current buffering and
see if removing them and rebuffering or incremental placement can work.
PnR tool does buffer to improve slews, reduce net capacitance and reduce fanout.

Incremental timing aware placement

Considering how important timing is, Tool recognizes and distributes cells to be closer together. It also removes
buffers.

Global or virtual or manhattan routing

To schedule the route available changes, there is a need to either start with Manhattan routing or with global routing. In addition, tools that estimate RC or congestion use either virtual routing, or models that simulate congestion estimation.

Congestion aware incremental coarse placement

If you indicate that a tool run studies and schedules on placement of the router’s cells into pipe, the tool will run a coarse placement stage, which will try to spread out the cells into different places and reduce congestion. This will not affect timing QoR.

Detail or legal placement

The placement phase is now complete. This is the last or in between of two steps of placement optimization.
Before these cells are placed, they are not snapped to their cell rows. Cells can also have minor overlaps.
Legalize placement will find the nearest full legal location for a cell to be placed.