Timing-Analysis,Debug and Fixing
Timing report analysis and debugging is difficult, but it may be learned with practise. Looking at the timing slack histograms, timing
reports in the following step, and the GUI will give you a good understanding of why this path is failing and what needs to be done
to correct it. There are so many alternatives that it may not be possible to discuss them all here.
Let us go through what could be the possible debug outcomes:
Constraints issue: In early design cycles for the products which are designed for the first might have some constraints issues. If you see some paths crossing multiple clock domains, half cycle path or zero cycle paths, high input, or output delays on IO paths etc and if you have access to designer, try to discuss such paths with them to see if they make sense.
Design or synthesis issue: if you see a path that is correctly placed on the die and a lot of logic levels from flop to flop. To find out if this is normal and whether logic levels can be lowered, you should talk about such paths with designers and synthesizers.
Placement issue: If you notice that cells in a path that are positioned far apart are interacting, you should consider why
this is happening. It is highly possible that you won't be able to quickly recommend what has to be done. As determining whether modules are correctly positioned or not depends on more than just the arrangement of a few cells. Additionally, you are unsure if moving some cells closer together will move other similarly situated cells farther away if you try to move them. So, it becomes difficult to determine this. The quickest way to learn would be if you knew something about design.
Over buffering or less buffering: Buffers are occasionally not added correctly. Either there is insufficient buffering, which
results in timing problems during setup, or there is too little buffering. Higher buffering may result from cells being spaced more apart or from the arrangement of cells along the path being scenic. This pertains to the placement-related difficulties that we have already covered. Mismatched tools and RC estimation may also be to blame. Tool calculates RC while it performs buffering. This estimate is based on measuring the length of the route. When it is applied, there is a good chance that average estimation will differ from true RC.
Global routing detours:If your design is congested, you'll see that nets are being diverted. Due to the long net length caused by this, timing problems are caused by faulty slews and delays. In order to resolve this problem, you must try to lessen congestion.
Improper Optimization: There are many causes, including improper cell sizing, the use of tiny drive cells, and significant
positioning changes as a result of legalization, among others. These problems can be resolved by an incremental timing
optimization step.